The present application relates generally to an improved data processing apparatus and method and more specifically to mechanisms for post timing layout modification for performance.
An integrated circuit (IC), also referred to as a chip or microchip, is an electronic circuit manufactured by the patterned diffusion of dopants into the surface of a thin substrate of semiconductor material. Integrated circuits are used in virtually all electronic equipment today and have revolutionized the world of electronics. Computers, cellular phones, and other digital appliances are now inextricable parts of the structure of modern societies, made possible by the low cost of production of integrated circuits. Very-large-scale integration (VLSI) is the process of creating integrated circuits by combining millions of transistors into a single chip.
Static timing analysis (STA) is a method of computing the expected timing of a digital circuit without requiring simulation. High-performance integrated circuits have traditionally been characterized by the clock frequency at which they operate. Gauging the ability of a circuit to operate at the specified speed requires ability to measure, during the design process, its delay at numerous steps. Moreover, delay calculation must be incorporated into the inner loop of timing optimizers at various phases of design, such as logic synthesis, layout (placement and routing), and in in-place optimizations performed late in the design cycle.
While such timing measurements can theoretically be performed using a rigorous circuit simulation, such an approach is liable to be too slow to be practical. Static timing analysis plays a vital role in facilitating the fast and reasonably accurate measurement of circuit timing. The speedup appears due to the use of simplified delay models, and on account of the fact that its ability to consider the effects of logical interactions between signals is limited.
Integrated circuits include many transistors. Commonly, transistors are metal-oxide-semiconductor field-effect transistor (MOSFET) devices. MOSFETs include a gate, source, and drain. The source and drain are connected to individual highly doped regions that are separated by the body region. These regions can be either p or n type, but they must both be of the same type, and of opposite type to the body region. These regions are often referred to as the p-well or n-well. If the MOSFET is an NFET, then the source and drain are ‘n+’ regions and the body is a ‘p’ region. If the MOSFET is a PFET, then the source and drain are ‘p+’ regions and the body is an ‘n’ region.
One may increase chip performance by adding layout structures to apply n-well stress, or p-well stress. Currently, this is done on each transistor regardless of its impact on timing. Device extraction is required because gate level timing would not see this effect. Yet, device extraction and transistor-level timing is not feasible on large scale circuits, such as chip units or complete chips, due to long run times. Also, the blind application of performance improvements to any timing path may cause hold-time violations in fast paths. Applying n-well or p-well stress increases the mobility of charge carriers, which increases switching speed, thus increasing performance.